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asix electronics corporation released date: 12/24/2007 4f, no.8, hsin ann rd., hsinchu science park, hsin-chu city, taiwan, r.o.c. 300 tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw/ ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller features single chip usb 2.0 to 10/100m fast ethernet controller ? ax88772a single chip usb 2.0 to mii, single chip mii to ethernet and usb bridging controller in dual-phy mode (submitted for us patent application) ? AX88172A usb device interface integrates on-chip usb 2.0 transceiver and sie compliant to usb spec 1.1 and 2.0 supports usb full and high speed modes with bus-power or self-power capability supports 4 or 6 programmable endpoints on usb interface high performance packet transfer rate over usb bus using proprietary burst transfer mechanism (submitted for us patent application) supports usb to ethernet bridging or vice versa in hardware fast ethernet controller integrates 10/100mbps fast ethernet mac/phy ieee 802.3 10base-t/100base-tx compatible supports twisted pair crossover detection and auto-correction (hp auto-mdix) embedded 16kb sram for rx packet buffering and 8kb sram for tx packet buffering supports both full-duplex with flow control and half-duplex with backpressure operation supports 2 vlan id filtering, received vlan tag (4 bytes) can be stripped off or preserved mac/phy loop-back diagnostic capability support wake-on-lan function supports suspend mode and remote wakeup via link-up, magic packet, ms wakeup frame and external pin optional phy power down during suspend mode versatile external media interface optional mii interface in mac mode allows AX88172A to work with external 100base-fx ethernet phy or homepna phy optional reverse-mii or reverse-rmii interface in phy mode allows AX88172A to work with external homeplug phy or glueless mac-to-mac connections optional reverse-mii interface in dual-phy mode allows AX88172A to act as an ethernet phy or usb 2.0 phy for external mac device that needs ethernet and usb in system application supports 256/512 bytes (93c56/93c66) of serial eeprom (for storing usb descriptors) supports automatic loading of ethernet id, usb descriptors and adapter configuration from eeprom after power-on initialization provides optional serial interface, i2c, spi and uart integrates on-chip voltage regulator and only requires a single 3.3v power supply 12mhz and 25mhz clock input from either crystal or oscillator source integrates on-chip power-on reset circuit small form factor with 64-pin lqfp (ax88772a) or 80-pin tqfp (AX88172A) rohs compliant package operating temperature range: 0 c to 70 c. *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller is a high performance and highly integrated asic which enables low cost, small form factor, and simple pl ug-and-play fast ethernet network connection capability for deskto ps, notebook pc?s, ultra-mobile pc?s, docking st ations, game consoles, digital-home app liances, and any embedded system using a standard usb port. the ax88772a/AX88172A features a usb interf ace to communicate with a usb host c ontroller and is compliant with usb specification v1.1 and v2.0. the ax88772a/AX88172A implements 10/100mbps ethernet lan func tion based on ieee802.3, and ieee802.3u standards with 24kb of embedded sram for pack et buffering. the ax88772a/AX88172A integrates an on-chip 10/100mbps ethernet phy to simplify system design. the AX88172A provides an optional external media interface (emi) fo r external phy or external mac for different application purposes. the emi can be a media-independe nt interface (mii) for implementing 100base-fx ethernet or homepna functions. the emi can also be a reverse-mii or revers e reduced-mii (reverse-rmii) for glueless ma c-to-mac connections to any mcu with ethernet mac mii or rmii interface. in addition, the emi can be configured to dual-phy mode allowing AX88172A to act as an ethernet phy or usb 2.0 phy for external mac device that needs ethernet and usb interfaces in their system applications. the optional serial interface such as i2c, spi, and uart are provided as a control channel from the usb host controller to communic ate with the external mcu chip. always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electr onics reserves the rights to m odify product speci fication without notice. no liability is assumed as a result of the us e of this product. no rights under any pa tent accompany the sale of the product. document no: ax88x72a/v1.1/12/24/07
asix electronics corporation 2 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller target applications pc/internet consumer electronics figure 1 : target applications pocketable computer usb dongle docking station card reader usb kvme switch internet security usb key port replicator for mobile computer uwb/802.11n/wimax usb dongle media gateway umpc portable media player epiano iptv ip stb tivo box game console dvd-recorder/dvr
asix electronics corporation 3 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller typical system block diagrams hosted by usb to operate with internal ethernet phy only figure 2 : usb 2.0 to lan adaptor (mac mode) hosted by usb to operate with either int ernal ethernet phy or emi (in mac mode) figure 3 : usb 2.0 to fast ethernet and 100base-fx fiber/homepna combo (mac mode) magnetic r j 45 spi i2c uart 100base fx phy fibe r homepna phy ma g netic r j 11 mii AX88172A eeprom mdc mdio to usb 2.0 host i/f or ethernet phy to usb 2.0 host i/f ax88772a eeprom magnetic r j 45 spi i2c uart ethernet phy
asix electronics corporation 4 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller hosted by usb to operate with either int ernal ethernet phy (in mac mode) or emi (in phy mode) figure 4 : bridging embedded mcu to usb 2.0 host interface (phy mode) figure 5 : usb 2.0 to homeplug adaptor (phy mode) to usb 2.0 host i/f AX88172A eeprom homeplug phy reverse-mii or reverse-rmii (no oscillator or buffer required) mdc mdio magnetic rj45 powerline ethernet phy to usb 2.0 host i/f AX88172A eeprom embedded mcu eth e rn e t ma c reverse-mii or reverse-rmii (no oscillator or buffer required) mdc mdio magnetic rj45 spi i2c uart ethernet phy
asix electronics corporation 5 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller hosted by emi to operate with either internal ethernet phy or usb phy (in dual-phy mode) figure 6 : bridging embedded mcu to eith er ethernet phy or usb 2.0 interface to usb 2.0 host i/f AX88172A eeprom reverse-mii (no oscillator or buffer required) mdc mdio magnetic rj45 spi i2c uart embedded mcu ethernet mac usb 2.0 device ethernet phy
asix electronics corporation 6 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller table of contents 1.0 introduction ................................................................................................................... 9 1.1 g eneral d escription ............................................................................................................................... ........ 9 1.2 b lock d iagram ............................................................................................................................... ................. 9 1.3 p inout d iagram ............................................................................................................................... ............... 10 2.0 signal description ........................................................................................... 14 2.1 ax88772a 64- pin p inout d escription ......................................................................................................... 14 2.2 AX88172A 80- pin p inout d escription ......................................................................................................... 16 2.3 h ardware s etting f or o peration m ode a nd m ulti -f unction p ins ...................................................... 20 3.0 function description ................................................................................. 20 3.1 usb c ore and i nterface .............................................................................................................................. 20 3.2 10/100m e thernet phy ............................................................................................................................ ..... 20 3.3 mac c ore ............................................................................................................................... ........................ 20 3.4 o peration m ode ............................................................................................................................... .............. 20 3.5 s tation m anagement (sta)......................................................................................................................... 20 3.6 m emory a rbiter ............................................................................................................................... ............. 20 3.7 usb to e thernet b ridge .............................................................................................................................. 20 3.8 s erial eeprom l oader ............................................................................................................................... 20 3.9 g eneral p urpose i/o............................................................................................................................ .......... 20 3.10 s erial i nterface c ontroller ...................................................................................................................... 20 3.11 c lock g eneration ............................................................................................................................... .......... 20 3.12 r eset g eneration ............................................................................................................................... ........... 20 3.13 v oltage r egulator ............................................................................................................................... ....... 20 4.0 serial eeprom memory map ........................................................ 20 4.1 d etailed d escription ............................................................................................................................... ..... 20 5.0 usb configuration structure .............................................. 20 5.1 usb c onfiguration ............................................................................................................................... ........ 20 5.2 usb i nterface ............................................................................................................................... ................. 20 5.3 usb e ndpoints ............................................................................................................................... ................ 20 6.0 usb commands ............................................................................................................... 20 6.1 usb s tandard c ommands ............................................................................................................................ 20 6.2 usb v endor c ommands ............................................................................................................................... . 20 6.2.1 detailed register description .................................................................................................. ................ 20 6.2.2 command block wrapper for serial interface ..................................................................................... .... 20 6.2.2.1 uart controller ............................................................................................................................... .. 20 6.2.2.2 i2c controller ............................................................................................................................... ....... 21 6.2.2.3 spi controller ............................................................................................................................... ....... 21 6.3 i nterrupt e ndpoint ............................................................................................................................... ........ 21 7.0 embedded ethernet phy register description ............................................................................................................................... ......... 21 7.1 phy r egister d etailed d escription ........................................................................................................... 21 7.1.1 basic mode control register (bmcr) ............................................................................................. ........ 21 7.1.2 basic mode status register (bmsr).............................................................................................. ........... 21 7.1.3 phy identifier re gister 1...................................................................................................... .................... 21
asix electronics corporation 7 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 7.1.4 phy identifier re gister 2...................................................................................................... .................... 21 7.1.5 auto negotiation advertisem ent register (anar) ................................................................................. .. 21 7.1.6 auto negotiation link partne r ability regist er (a nlpar) ..................................................................... 21 7.1.7 auto negotiation expansi on register (aner) ..................................................................................... .... 21 8.0 station management registers in phy/dual-phy mode ........................................................................................................... 21 8.1 phy/d ual -phy m ode d etailed r egister d escription ............................................................................ 21 8.1.1 phy mode basic mode cont rol register (pm_bmcr)........................................................................... 21 8.1.2 phy mode basic mode stat us register (pm_bmsr) .............................................................................. 21 8.1.3 phy mode phy iden tifier regist er 1 ............................................................................................. .......... 21 8.1.4 phy mode phy iden tifier regist er 2 ............................................................................................. .......... 21 8.1.5 phy mode auto negotiation adver tisement regist er (pm_anar) ......................................................... 21 8.1.6 phy mode auto negotiation link pa rtner ability regist er (pm_anlpar) ........................................... 21 8.1.7 phy mode auto negotiation ex pansion register (pm_aner) ............................................................... 21 8.1.8 phy mode control regi ster (pm_control) ......................................................................................... .... 21 9.0 electrical specifications ............................................................ 22 9.1 dc c haracteristics ............................................................................................................................... ....... 22 9.1.1 absolute maximum ratings ....................................................................................................... ............... 22 9.1.2 recommended operating condition................................................................................................ ......... 22 9.1.3 leakage current and capacitance ................................................................................................ ........... 23 9.1.4 dc characteristics of 3.3v i/o pins ............................................................................................ ............ 23 9.1.5 dc characteristics of 3.3v with 5v tolerance i/o pins.......................................................................... 24 9.1.6 dc characteristics of voltage regulator........................................................................................ ......... 25 9.2 p ower c onsumption ............................................................................................................................... ....... 26 9.3 p ower - up s equence ............................................................................................................................... ........ 27 9.4 ac t iming c haracteristics .......................................................................................................................... 28 9.4.1 clock timing................................................................................................................... .......................... 28 9.4.2 reset ti ming ................................................................................................................... .......................... 28 9.4.3 serial eepro m timing........................................................................................................... ................. 29 9.4.4 mii timing ..................................................................................................................... ........................... 30 9.4.5 station manageme nt timing...................................................................................................... ............... 31 9.4.6 reverse-mii timing ............................................................................................................. ..................... 32 9.4.7 reverse-rmii timing............................................................................................................ .................... 33 9.4.8 i2c interfa ce timing........................................................................................................... ...................... 34 9.4.9 spi interface timing........................................................................................................... ...................... 35 9.4.10 10/100m ethernet phy interface timing .......................................................................................... ....... 37 9.4.11 usb transceiver in terface timing ............................................................................................... ............ 38 10.0 package information ........................................................................... 40 10.1 ax88772a 64- pin lqfp package .................................................................................................................. 40 10.2 AX88172A 80- pin tqfp package .................................................................................................................. 41 11.0 ordering information ........................................................................ 42 12.0 revision history ................................................................................................ 43 appendix a. default wol ready mode .................................................................... 44
asix electronics corporation 8 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller list of figures f igure 1 : t arget a pplications ............................................................................................................................... .. 2 f igure 2 : usb 2.0 to lan a daptor (mac mode )................................................................................................... 3 f igure 3 : usb 2.0 to f ast e thernet and 100base-fx f iber /h ome pna c ombo (mac mode ) ........................ 3 f igure 4 : b ridging e mbedded mcu to usb 2.0 h ost i nterface (phy mode ).................................................... 4 f igure 5 : usb 2.0 to h ome p lug a daptor (phy mode ).......................................................................................... 4 f igure 6 : b ridging e mbedded mcu to either e thernet phy or usb 2.0 i nterface ....................................... 5 f igure 7 : ax88772a/AX88172A b lock d iagram ................................................................................................... 9 f igure 8 : ax88772a p inout d iagram (mac mode without mii)....................................................................... 10 f igure 9 : AX88172A p inout d iagram (mac mode with mii) ............................................................................. 11 f igure 10 : AX88172A p inout d iagram (phy mode with r everse -mii) .......................................................... 12 f igure 11 : AX88172A p inout d iagram (phy mode with r everse -rmii)........................................................ 13 list of tables t able 1 : ax88772a 64- pin p inout d escription ................................................................................................... 14 t able 2 : AX88172A 80- pin p inout d escription ................................................................................................... 16 t able 3 : p ower consumption ............................................................................................................................... .. 26
asix electronics corporation 9 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 1.0 introduction 1.1 general description the ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller is a high performance and highly integrated asic which enables low cost, small form factor, and simple plug-and-play fast ethernet network connection capability for desktops, note book pc?s, ultra-mobile pc?s, docking st ations, game consoles, digital-home appliances, and any embedded system using a standard usb port. the ax88772a/AX88172A features a usb interface to communicate with a usb host controller and is compliant with usb specification v1.1 and v2.0. the ax88772a/AX88172A implements a 10/100mbps ethernet lan function based on ieee802.3, and ieee802.3u standards with 24kb of embedded sram for packet buffering. the ax88772a/AX88172A integrates an on-chip 10/100mbps ethernet phy to simplify system design. the AX88172A provides an optional external media interface (emi) for external phy or external mac for different application purposes. the emi can be a media-independent interface (mii) for implementing 100base-fx ethernet or homepna functions. the emi can also be a reverse-m ii or reverse reduced-mii (r everse-rmii) for glueless mac-to-mac connections to any mcu with ethernet mac mii or rmii inte rface. in addition, the emi can be configured to dual-phy mode allowing AX88172A to act as an ethernet phy or usb 2.0 phy for external mac device that needs ethernet and usb interfaces in their system applications. the optional serial interface such as i2c, spi, and uart are provided as a control channel from the usb host controller to communicate with the external mcu chip. the ax88772a/AX88172A needs 12mhz clock for usb operation and 25mhz clock for fast ethernet operation. the ax88772a is housed in the 64-pin lqfp and the AX88172A is housed in the 80-pin tqfp rohs compliant package. 1.2 block diagram figure 7 : ax88772a/AX88172A block diagram dp/dm rxip/rxin txop/txon gpio_2~0 mac core memory arbiter usb to ethernet bridge usb core and interfaces sta seeprom loader i/f eecs eeck eedio 24kb sram general purpose i/o 10/100m ethernet phy serial i/f controller: uart/i2c/spi si_3~0 AX88172A only external media interface mii / reverse-mii / reverse-rmii mdc / mdio 3.3 to 1.8v regulator pll clock generators power-on-reset & reset gen. reset_n xtl25p, xtl25n xtl12p, xtl12n phy/mac mode bridge
asix electronics corporation 10 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 1.3 pinout diagram ax88772a in 64-pin lqfp package v_bus vcck gnd gnd test0 test1 reset_n vcc3io tclk_en tclk_0 tclk_1 eedio eecs eeck gnd vcck 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 vcc3io 49 32 si_0 vcck 50 31 si_1 xtl12p 51 30 si_2 xtl12n 52 29 si_3 vcc33a_h 53 28 gpio_0 / pme gnd33a_h 54 27 gpio_1 rref 55 26 gpio_2 dm 56 25 vcck dp 57 24 extwakeup_n vcc33a_pll 58 23 gnd gnd33a_pll 59 22 usb_led gnd 60 21 vcck vcc18a 61 20 link_led xtl25p 62 19 speed_led xtl25n 63 18 fdx_led gnd18a 64 ax88772a (mac mode without mii) 17 vcc3io 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rset_bg vcc3a3 gnd3a3 rxip rxin vcc18a txop txon gnd18a v18f vcc3r3 gnd3r3 vcck vcck gnd gnd figure 8 : ax88772a pinout diagram (mac mode without mii)
asix electronics corporation 11 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller AX88172A in 80-pin tqfp package - mac mode with mii figure 9 : AX88172A pinout diagram (mac mode with mii) txd2 txd3 v_bus vcck gnd gnd test0 test1 reset_n vcc3io tclk_en tclk_0 tclk_1 eedio eecs eeck mdc mdio gnd vcck 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 txd1 61 40 si_0 txd0 62 39 si_1 txclk 63 38 si_2 txen 64 37 si_3 vcc3io 65 36 gpio_0 / pme vcck 66 35 gpio_1 xtl12p 67 34 gpio_2 xtl12n 68 33 vcck vcc33a_h 69 32 col gnd33a_h 70 31 crs rref 71 30 extwakeup_n dm 72 29 gnd dp 73 28 usb_led vcc33a_pll 74 27 vcck gnd33a_pll 75 26 link_led gnd 76 25 speed_led vcc18a 77 24 fdx_led xtl25p 78 23 rxd0 xtl25n 79 22 rxd1 gnd18a 80 AX88172A (mac mode with mii) 21 vcc3io 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 rset_bg vcc3a3 gnd3a3 rxip rxin vcc18a txop txon gnd18a v18f vcc3r3 gnd3r3 vcck vcck gnd gnd rxclk rxdv rxd3 rxd2
asix electronics corporation 12 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller AX88172A in 80-pin tqfp package - phy mode with reverse-mii figure 10 : AX88172A pinout diagram (phy mode with reverse-mii) rxd2 rxd3 v_bus vcck gnd gnd test0 test1 reset_n vcc3io tclk_en tclk_0 tclk_1 eedio eecs eeck mdc mdio gnd vcck 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 rxd1 61 40 si_0 rxd0 62 39 si_1 rxclk 63 38 si_2 rxdv 64 37 si_3 vcc3io 65 36 gpio_0 / pme vcck 66 35 gpio_1 xtl12p 67 34 rxer xtl12n 68 33 vcck vcc33a_h 69 32 col gnd33a_h 70 31 crs rref 71 30 extwakeup_n dm 72 29 gnd dp 73 28 usb_led vcc33a_pll 74 27 vcck gnd33a_pll 75 26 link_led gnd 76 25 speed_led vcc18a 77 24 fdx_led xtl25p 78 23 txd0 xtl25n 79 22 txd1 gnd18a 80 AX88172A (phy mode with reverse-mii) 21 vcc3io 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 rset_bg vcc3a3 gnd3a3 rxip rxin vcc18a txop txon gnd18a v18f vcc3r3 gnd3r3 vcck vcck gnd gnd txclk txen txd3 txd2
asix electronics corporation 13 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller AX88172A in 80-pin tqfp package - phy mode with reverse-rmii mis_0 mis_1 v_bus vcck gnd gnd test0 test1 reset_n vcc3io tclk_en tclk_0 tclk_1 eedio eecs eeck mdc mdio gnd vcck 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 rxd1 61 40 si_0 rxd0 62 39 si_1 refclk_o 63 38 si_2 crsdv 64 37 si_3 vcc3io 65 36 gpio_0 / pme vcck 66 35 gpio_1 xtl12p 67 34 rxer xtl12n 68 33 vcck vcc33a_h 69 32 nc gnd33a_h 70 31 nc rref 71 30 extwakeup_n dm 72 29 gnd dp 73 28 usb_led vcc33a_pll 74 27 vcck gnd33a_pll 75 26 link_led gnd 76 25 speed_led vcc18a 77 24 fdx_led xtl25p 78 23 txd0 xtl25n 79 22 txd1 gndk18a 80 AX88172A (phy mode with reverse-rmii) 21 vcc3io 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 rset_bg vcc3a3 gnd3a3 rxip rxin vcc18a txop txon gnd18a v18f vcc3r3 gnd3r3 vcck vcck gnd gnd refclk_i txen nc nc figure 11 : AX88172A pinout diagram (phy mode with reverse-rmii)
asix electronics corporation 14 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 2.0 signal description the following abbreviations apply to the following pin description table. i18 input, 1.8v ao analog output i3 input, 3.3v ab analog bi-directional i/o i5 input, 3.3v with 5v tolerant pu internal pull up (75k) o3 output, 3.3v pd internal pull down (75k) o5 output, 3.3v with 5v tolerant p power pin b5 bi-directional i/o, 3.3v with 5v tolerant s t schmitt trigger tri-stateable ai analog input note: every output or bi-directional i/o pin is 8ma driving strength. 2.1 ax88772a 64-pin pinout description table 1 : ax88772a 64-pin pinout description pin name type pin no pin description usb interface dp ab 57 usb 2.0 data positive pin. dm ab 56 usb 2.0 data negative pin. vbus i5/pd/s 48 vbus pin input. please connect to usb bus power. xtl12p i3 51 12mhz 0.003%crystal or oscillator clock i nput. this clock is needed for usb phy transceiver to operate. xtl12n o3 52 12mhz crystal or oscillator clock output. rref ai 55 for usb phy?s internal biasing. please connect to analog gnd through a resistor (12.1kohm 1%). serial eeprom interface eeck b5/pd/ t 35 eeprom clock. eeck is an output clock to eeprom to provide timing reference for the transfer of eecs, and eedio signals. eeck only drive high / low when access eeprom otherwise keep at tri-state and internal pull-down. eecs b5/pd/ t 36 eeprom chip select. eecs is asserted high synchronously with respect to rising edge of eeck as chip select signal. eecs only drive high / low when access eeprom otherwise keep at tr i-state and internal pull-down. eedio b5/pu/ t 37 eeprom data in. eedio is the serial output data to eeprom?s data input pin and is synchronous with respect to the rising edge of eeck. eedio only drive high / low when access eeprom otherwise keep at tri-state and internal pull-up. ethernet phy interface xtl25p i18 62 25mhz 0.005% crystal or oscillator clock input. this clock is needed for the embedded 10/100m ethernet phy to operate. xtl25n o18 63 25mhz crystal or oscillator clock output. rxip ab 4 receive data input positiv e pin for both 10base-t and 100base-tx. rxin ab 5 receive data input negativ e pin for both 10base-t and 100base-tx. txop ab 7 transmit data output positiv e pin for both 10base-t and 100 base-tx txon ab 8 transmit data output negativ e pin for both 10base-t and 100 base-tx rset_bg ao 1 for ethernet phy?s internal biasing. please connect to gnd through a 12.1kohm 1% resistor. link_led o5 20 link status led indicator. this pin drives low continuously when the ethernet link is up and drives low and high in turn (blinking) when ethernet phy is in receiving or transmitting state.
asix electronics corporation 15 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller fdx_led o5 18 full duplex and collision detected led indicator. this pin drives low when the ethernet phy is in full-duplex mode and drives high when in half duplex mode. when in half duplex mode and the ethernet phy detects collision, it will be driven low (or blinking). speed_led o5 19 ethernet speed led indicator. this pin drives low when the ethernet phy is in 100base-tx mode and drives high when in 10base-t mode. misc. pins reset_n i5/pu/s 42 chip reset input. active low. this is the external reset source used to reset this chip. this input feeds to the internal power-on reset circuitry, which provides the main reset source of this chip. after completing reset, eeprom data will be loaded automatically. extwakeup_n i5/pu/s 24 remote-wakeup trigger from external pin. extwakeup_n should be asserted low for more than 2 cycles of 12mhz clock to be effective. gpio_2 b5/pd 26 general purpose input/ output pin 2. gpio_1 b5/pd 27 general purpose input/ output pin 1. this pin is default as input pin after power-on reset. this pin is also for default wol ready mode setting; please refer to section 2.3 settings. gpio_0/pme b5/pd 28 general purpose input/ output pin 0 or pme (power management event). this pin is default as input pin after power-on reset. gpio_0 also can be defined as pme output to indicate wak e up event detected. please refer to section 2.3 settings. si_3 b5/pu 29 uart_rx or spi_miso. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. si_2 b5/pu 30 uart_tx or spi_mosi. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. si_1 b5/pu 31 i2c_sda or spi_ss. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. si_0 b5/pu 32 i2c_sclk or spi_sclk. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. usb_led o5 22 usb speed indicator: when usb bus is in full speed, this pin drives high continuously. when usb bus is in high speed, this pin drives low continuously. this pin drives high and low in turn (blinking) to indicate tx data transfer going on whenever the host controller sends bulk out data transfer. test0 i5/s 44 test pin. for normal operation, user should connect to ground. test1 i5/s 43 test pin. for normal operation, user should connect to ground. tclk_en i5/pd/s 40 test pin. for normal operation, user should keep this pin nc. tclk_0 i5/pd 39 test pin. for normal operation, user should keep this pin nc. tclk_1 i5/pd 38 test pin. for normal operation, user should keep this pin nc. on-chip regulator pins vcc3r3 p 11 3.3v power supply to on-chip 3.3v to 1.8v voltage regulator. gnd3r3 p 12 ground pin of on-chip 3.3v to 1.8v voltage regulator. v18f p 10 1.8v voltage output of on-chip 3.3v to 1.8v voltage regulator. power and ground pins vcck p 13, 14, 21, 25, 33, 47, 50 digital core power. 1.8v. vcc3io p 17, 41, 49 digital i/o power. 3.3v. gnd p 15, 16, 23, 34, 45, 46, 60 digital ground. vcc33a_h p 53 analog power for usb transceiver. 3.3v. gnd33a_h p 54 analog ground for usb transceiver. vcc33a_pll p 58 analog power for usb pll. 3.3v. gnd33a_pll p 59 analog ground for usb pll. vcc3a3 p 2 analog power for ethernet phy bandgap. 3.3v. gnd3a3 p 3 analog ground for ethernet phy. vcc18a p 6, 61 analog power for ethernet phy and 25mhz crystal oscillator. 1.8v.
asix electronics corporation 16 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller gnd18a p 9, 64 analog ground for ethernet phy and 25mhz crystal oscillator. 2.2 AX88172A 80-pin pinout description table 2 : AX88172A 80-pin pinout description pin name type pin no pin description usb interface dp ab 73 usb 2.0 data positive pin. dm ab 72 usb 2.0 data negative pin. vbus i5/pd/s 58 vbus pin input. please connect to usb bus power. xtl12p i3 67 12mhz 0.003%crystal or oscillator clock i nput. this clock is needed for usb phy transceiver to operate. xtl12n o3 68 12mhz crystal or oscillator clock output. rref ai 71 for usb phy?s internal biasing. please connect to analog gnd through a resistor (12.1kohm 1%). serial eeprom interface eeck b5/pd/ t 45 eeprom clock. eeck is an output clock to eeprom to provide timing reference for the transfer of eecs, and eedio signals. eeck only drive high / low when access eeprom otherwise keep at tri-state and internal pull-down. eecs b5/pd/ t 46 eeprom chip select. eecs is asserted high synchronously with respect to rising edge of eeck as chip select signal. eecs only drive high / low when access eeprom otherwise keep at tri-state and internal pull-down. eedio b5/pu/ t 47 eeprom data in. eedio is the serial output data to eeprom?s data input pin and is synchronous with respect to the rising edge of eeck. eedio only drive high / low when access eeprom otherwise keep at tri-state and internal pull-up. ethernet phy interface xtl25p i18 78 25mhz 0.005% crystal or oscillator clock input. this clock is needed for the embedded 10/100m ethernet phy to operate. xtl25n o18 79 25mhz crystal or oscillator clock output. rxip ab 4 receive data input positiv e pin for both 10base-t and 100base-tx. rxin ab 5 receive data input negativ e pin for both 10base-t and 100base-tx. txop ab 7 transmit data output positiv e pin for both 10base-t and 100 base-tx txon ab 8 transmit data output negativ e pin for both 10base-t and 100 base-tx rset_bg ao 1 for ethernet phy?s internal biasing. please connect to gnd through a 12.1kohm 1% resistor. link_led o5 26 link status led indicator. this pin drives low continuously when the ethernet link is up and drives low and high in turn (blinking) when ethernet phy is in recei ving or transmitting state. fdx_led o5 24 full duplex and collision detected led indicator. this pin drives low when the ethernet phy is in full-duplex mode and drives high when in half duplex mode. when in half duplex mode and the ethernet phy detects collision, it will be driven low (or blinking). speed_led o5 25 ethernet speed led indicator. this pin drives low when the ethernet phy is in 100base-tx mode and drives high when in 10base-t mode. misc. pins reset_n i5/pu/s 52 chip reset input. reset_n pin is active low. when asserted, it puts the entire chip into reset state immediately. after completing reset, eeprom data will be loaded automatically. extwakeup_n i5/pu/s 30 remote-wakeup trigger from external pin. extwakeup_n should be asserted low for more than 2 cycles of 12mhz clock to be effective. gpio_2 / rxer b5/pd 34 general purpose input/ output pin 2. this pin is gpio_2 in mac mode, but it will be redefined as rxer (r eceive error) or gpio_2 depending on eeprom flag [3] in phy mode.
asix electronics corporation 17 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller gpio_1 b5/pd 35 general purpose input/ output pin 1. this pin is default as input pin after power-on reset. this pin is also for default wol ready mode setting; please refer to section 2.3 settings. gpio_0 / pme b5/pd 36 general purpose input/ output pin 0 or pme (power management event). this pin is default as input pin after power-on reset. gpio_0 also can be defined as pme output to indicate wak e up event detected. please refer to section 2.3 settings. si_3 b5/pu 37 uart_rx or spi_miso. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. si_2 b5/pu 38 uart_tx or spi_mosi. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. si_1 b5/pu 39 i2c_sda or spi_ss. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. si_0 b5/pu 40 i2c_sclk or spi_sclk. this is a multi-function pin determined by eeprom flag [1] setting. please refer to section 2.3 settings. usb_led o5 28 usb speed indicator: when usb bus is in full speed, this pin drives high continuously. when usb bus is in high speed, this pin drives low continuously. this pin drives high and low in turn (blinking) to indicate tx data transfer going on whenever the host controller sends bulk out data transfer. test0 i5/s 54 test pin. for normal operation, user should connect to ground. test1 i5/s 53 test pin. for normal operation, user should connect to ground. tclk_en i5/pd/s 50 test pin. for normal operation, user should keep this pin nc. tclk_0 i5/pd 49 test pin. for normal operation, user should keep this pin nc. tclk_1 i5/pd 48 test pin. for normal operation, user should keep this pin nc. on-chip regulator pins vcc3r3 p 11 3.3v power supply to on-chip 3.3v-to-1.8v voltage regulator. gnd3r3 p 12 ground pin of on-chip 3.3v-to-1.8v voltage regulator. v18f p 10 1.8v voltage output of on-chip 3.3v-to-1.8v voltage regulator. power and ground pins vcck p 13, 14, 27, 33, 41, 57, 66, digital core power. 1.8v. vcc3io p 21, 51, 65 digital i/o power. 3.3v. gnd p 15, 16, 29, 42, 55, 56, 76 digital ground. vcc33a_h p 69 analog power for usb transceiver. 3.3v. gnd33a_h p 70 analog ground for usb transceiver. vcc33a_pll p 74 analog power for usb pll. 3.3v. gnd33a_pll p 75 analog ground for usb pll. vcc3a3 p 2 analog power for ethernet phy bandgap. 3.3v. gnd3a3 p 3 analog ground for ethernet phy. vcc18a p 6, 77 analog power for ethernet phy and 25mhz crystal oscillator. 1.8v. gnd18a p 9, 80 analog ground for ethernet phy and 25mhz crystal oscillator. external media interface: m ac mode with mii interface rxclk i5/pd 17 receive clock. rxclk is received from phy to p rovide timing reference for the transfer of rxd [3:0] and rxdv signals on recei ve direction of mii interface. rxdv i5/pd 18 receive data valid. rxdv is asserted high when valid data is present on rxd [3:0]. it is driven synchronously with respect to rxclk by phy. rxd [3:0] i5/pd 19, 20, 22, 23 receive data. rxd [3:0] is driven synchronously with respect to rxclk by phy. crs i5/pd 31 carrier sense. crs is asserted high asynchronously by the phy when either transmit or receive medium is non-idle. col i5/pd 32 collision. col is driven high by phy when the collision is detected.
asix electronics corporation 18 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller txclk i5/pd 63 transmit clock. txclk is received from phy to provide timing reference for the transfer of txd [3:0] and txen signals on transmit direction of mii interface. txen o3 64 transmit enable. txen is asserted high to indicate a valid txd [3:0]. it is transitioned synchronously with respect to the rising edge of txclk. txd [3:0] o3 59, 60, 61, 62 transmit data. txd [3:0] is transitioned synchronously with respect to the rising edge of txclk. note t xd [3:2] are also used as chip operation mode selection pins; please refer to section 2.3 settings . mdc o3/pd 44 station management clock output to phy. all data transferred on mdio are synchronized to the rising edge of this clock. the frequency of mdc is 1.5mhz. mdio b5/pu 43 station management data input/output. serial data input/output transferred from/to the phys. the transfer prot ocol conforms to the ieee 802.3u mii spec. external media interface: phy mo de with reverse-mii interface txclk o3/t 17 transmit clock. this clock is provided to supply to the tx_clk of externally connected ethernet mac devi ce with mii. this pin is tri-stated in isolate mode. txen i5/pd 18 transmit enable. txen is asserted high to indicate a valid txd [3:0]. it should be driven synchronously with respect to the rising edge of txclk by the externally connected et hernet mac device with mii. txd [3:0] i5/pd 19, 20, 22, 23 transmit data. txd [3:0] should be driven synchronously with respect to the rising edge of txclk by the ex ternally connected ethernet mac device with mii. crs o3/pd/t 31 carrier sense. crs is asserted high by AX88172A when rxdv is asserted high in reverse-mii mode. this pin is tri-stated in isolate mode. col o3/pd/t 32 collision. col is always dr iven low because AX88172A is operating in 100m/full-duplex mode internally in reverse-mii mode. this pin is tri-stated in isolate mode. rxer o3/pd/t 34 receive error. rxer is al ways driven low by AX88172A in reverse-mii mode. this pin is tri-stated in isolate mode. rxclk o3/t 63 receive clock. this clock is provided to supply to the rx_clk of externally connected ethernet mac devi ce with mii. this pin is tri-stated in isolate mode. rxdv o3/t 64 receive data valid. rxdv is asse rted high when valid data is present on rxd [3:0]. it is transitioned synchronously with respect to rxclk from AX88172A to the externally connected ethernet mac device with mii. this pin is tri-stated in isolate mode. rxd [3:0] o3/t 59, 60, 61, 62 receive data. rxd [3:0] is transiti oned synchronously with respect to rxclk from AX88172A to the externally connected ethernet mac device with mii. note that rxd [3:2 ] are also used as chip operation mode selection pins. please refer to section 2.3 settings . these pins are tri-stated in isolate mode. mdc i5/pd 44 station management clock input from the externally connected ethernet mac device. all data transferred on mdio are synchronized to the rising edge of this clock. mdio b5/pu 43 station management data. serial data input/output transferred from/to the externally connected mac device. the transfer protocol should conform to the ieee 802.3u mii spec. external media interface: phy mo de with reverse-rmii interface refclk_i i5 17 50mhz +/-50ppm reference clock input for rmii receive, transmit and control signals. if externally connected ethe rnet mac device with rmii can?t provide 50mhz reference clock to AX88172A, then user can connect this pin to refclk_o and use refclk_o to supply clock to the externally connected ethernet mac device at the same time.
asix electronics corporation 19 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller txen i5/pd 18 transmit enable from the extern ally connected ethernet mac device with rmii. txd [1:0] i5/pd 22, 23 transmit data from the externally connected ethernet mac device with rmii. nc i5/pd 19, 20 nc nc o3/pd 31, 32 nc rxer o3/pd/t 34 receive error. rxer is always driven low by AX88172A in reverse-rmii mode. this pin is tri-stated in isolate mode. mis_1 i5/pd 59 external media interface select 1. this is used as chip operation mode selection pin; please refer to section 2.3 settings . mis_0 i5/pd 60 external media interface select 0. this is used as chip operation mode selection pin; please refer to section 2.3 settings . refclk_o o3 63 50mhz reference clock output. if the externally connected ethernet mac device can?t supply 50mhz reference clock, this clock can be used to supply to the ref_clk of externally connected ethernet mac device with rmii and the refclk_i of this chip. crsdv o3/t 64 carrier sense and receive data va lid to the externally connected ethernet mac device with rmii. this pin is tri-stated in isolate mode. rxd [1:0] o3/t 61, 62 receive data to the ex ternally connected ethernet mac device with rmii. these pins are tri-stated in isolate mode. mdc i5/pd 44 station management clock input from the externally connected ethernet mac device. all data transferred on mdio are synchronized to the rising edge of this clock. mdio b5/pu 43 station management data. serial data input/output transferred from/to the externally connected mac device. the transfer protocol should conform to the ieee 802.3u mii spec.
asix electronics corporation 20 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 2.3 hardware setting for operation mode and multi-function pins please contact asix for recei ving ?ax88x72a full datasheet? wh ich contains detailed descri ption of section 2.3 and section 3, 4, 5, 6, 7, 8. 3.0 function description 3.1 usb core and interface 3.2 10/100m ethernet phy 3.3 mac core 3.4 operation mode 3.5 station management (sta) 3.6 memory arbiter 3.7 usb to ethernet bridge 3.8 serial eeprom loader 3.9 general purpose i/o 3.10 serial interface controller 3.11 clock generation 3.12 reset generation 3.13 voltage regulator 4.0 serial eeprom memory map 4.1 detailed description 5.0 usb configuration structure 5.1 usb configuration 5.2 usb interface 5.3 usb endpoints 6.0 usb commands 6.1 usb standard commands 6.2 usb vendor commands 6.2.1 detailed register description 6.2.2 command block wrapper for serial interface 6.2.2.1 uart controller
asix electronics corporation 21 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 6.2.2.2 i2c controller 6.2.2.3 spi controller 6.3 interrupt endpoint 7.0 embedded ethernet phy register description 7.1 phy register detailed description 7.1.1 basic mode control register (bmcr) 7.1.2 basic mode status register (bmsr) 7.1.3 phy identifier register 1 7.1.4 phy identifier register 2 7.1.5 auto negotiation advertisement register (anar) 7.1.6 auto negotiation link part ner ability register (anlpar) 7.1.7 auto negotiation expansion register (aner) 8.0 station management registers in phy/dual-phy mode 8.1 phy/dual-phy mode detailed register description 8.1.1 phy mode basic mode control register (pm_bmcr) 8.1.2 phy mode basic mode status register (pm_bmsr) 8.1.3 phy mode phy identifier register 1 8.1.4 phy mode phy identifier register 2 8.1.5 phy mode auto negotiation advertisement register (pm_anar) 8.1.6 phy mode auto negotiation link partner ability register (pm_anlpar) 8.1.7 phy mode auto negotiation expansion register (pm_aner) 8.1.8 phy mode control register (pm_control)
asix electronics corporation 22 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.0 electrical specifications 9.1 dc characteristics 9.1.1 absolute maximum ratings symbol parameter rating unit vcck digital core power supply - 0.3 to 2.16 v vcc18a analog power. 1.8v - 0.3 to 2.16 v vcc3io power supply of 3.3v i/o - 0.3 to 4 v vcc3r3 power supply of on-chip voltage regulator - 0.3 to 4 v vcc3a3 analog power 3.3v for ethernet phy bandgap - 0.3 to 3.8 v vcc33a_pll analog power 3.3v for usb pll. - 0.3 to 4 v vcc33a_h analog power 3.3v for usb tx and rx - 0.3 to 4 v v in18 input voltage of 1.8v i/o - 0.3 to 2.16 v input voltage of 3.3v i/o - 0.3 to 4.0 v v in3 input voltage of 3.3v i/o with 5v tolerant - 0.3 to 5.8 v t stg storage temperature - 40 to 150 i in dc input current 20 ma i out output short circuit current 20 ma note: permanent device damage may occu r if absolute maximum ratings are exceeded. functional operation should be restricted to the optional sections of this datasheet. exposure to absolute ma ximum rating condition for extended periods may affect device reliability. 9.1.2 recommended operating condition symbol parameter min typ max unit vcck digital core power supply 1.62 1.8 1.98 v vcc18a analog core power supply 1.62 1.8 1.98 v vcc3r3 power supply of on-chip voltage regulator 2.97 3.3 3.63 v vcc3io power supply of 3.3v i/o 2.97 3.3 3.63 v vcc33a_h analog power 3.3v for usb tx and rx 2.97 3.3 3.63 v vcc33a_pll analog power 3.3v for usb pll. 2.97 3.3 3.63 v vcc3a3 analog power supply for bandgap 2.97 3.3 3.63 v v in18 input voltage of 1.8 v i/o 0 1.8 1.98 v input voltage of 3.3 v i/o 0 3.3 3.63 v v in3 input voltage of 3.3 v i/o with 5v tolerance 0 3.3 5.25 v t j commercial junction operating temperature 0 25 125 t a commercial operating temperature 0 - 70 z thermal characteristics symbol parameter rating unit lqfp 64(ax88772a) 13.1 c/w jc thermal resistance of junction to case tqfp 80(AX88172A) 27.5 c/w still air,lqfp 64(ax88772a) 45.1 c/w ja thermal resistance of junction to ambient still air,tqfp 80(AX88172A) 55.2 c/w
asix electronics corporation 23 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.1.3 leakage current and capacitance symbol parameter conditions min typ max unit i in input current no pull-up or pull-down -10 1 10 a i oz tri-state leakage current -10 1 10 a c in input capacitance - 2.2 - pf c out output capacitance - 2.2 - pf c bid bi-directional buffer capacitance - 2.2 - pf note: the capacitance listed above does not include pad cap acitance and package capacitance. one can estimate pin capacitance by adding a pad capacitance of about 0.5pf to the package capacitance. 9.1.4 dc characteristics of 3.3v i/o pins symbol parameter conditions min typ max unit vcc3io power supply of 3.3v i/o 3.3v i/o 2.97 3.3 3.63 v tj junction temperature 0 25 125 vil input low voltage - - 0.8 v vih input high voltage 2.0 - - v vt switching threshold lvttl 1.5 v vt- schmitt trigger negative going threshold voltage 0.8 1.1 - v vt+ schmitt trigger positive going threshold voltage lvttl - 1.6 2.0 v vol output low voltage iol = 8ma - - 0.4 v voh output high voltage ioh = -8ma 2.4 - - v rpu input pull-up resistance v in = 0 40 75 190 k rpd input pull-down resistance v in = vcc3i o 40 75 190 k input leakage current vin = vcc3io or 0 -10 1 10 a input leakage current with pull-up resistance vin = 0 -15 -45 -85 a iin input leakage current with pull-down resistance vin = vcc3io 15 45 85 a i oz tri-state output leakage current -10 1 10 a
asix electronics corporation 24 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.1.5 dc characteristics of 3.3v with 5v tolerance i/o pins symbol parameter conditions min typ max unit vcc3io power supply of 3.3v i/o 3.3v i/o 2.97 3.3 3.63 v tj junction temperature 0 25 125 vil input low voltage - - 0.8 v vih input high voltage 2.0 - - v vt switching threshold lvttl 1.5 v vt- schmitt trigger negative going threshold voltage 0.8 1.1 - v vt+ schmitt trigger positive going threshold voltage lvttl - 1.6 2.0 v vol output low voltage iol = 8ma - - 0.4 v voh output high voltage ioh = -8ma 2.4 - - v rpu input pull-up resistance v in = 0 40 75 190 k rpd input pull-down resistance v in = vcc3i o 40 75 190 k input leakage current vin = 5.5v or 0 5 a input leakage current with pull-up resistance vin = 0 -15 -45 -85 a iin input leakage current with pull-down resistance vin = vcc3io 15 45 85 a i oz tri-state output leakage current v in = 5.5v or 0 10 a
asix electronics corporation 25 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.1.6 dc characteristics of voltage regulator symbol description conditions min typ max unit vcc3r3 power supply of on-chip voltage regulator. 3.0 3.3 3.6 v tj operating junction temperature. 0 25 125 normal operation - - 240 ma iload driving current. standby mode enabled - - 30 ma v18f output voltage of on-chip voltage regulator. vcc3r3 = 3.3v 1.71 1.8 1.89 v vdrop dropout voltage. v18f = -1%, iload = 10ma - 0.1 0.2 v v18f (vcc3r3 x v18f) line regulation. vcc3r3 = 3.3v, iload = 50ma - 0.2 0.4 %/v v18f (iload x v18f) load regulation. vcc3r3 = 3.3v, 1ma Q iload Q 240ma - 0.02 0.05 %/ma v18f tj temperature coefficient. vcc3r3 = 3.3v,-40 Q tj Q 125 - +/-0.2 +/-0.5 mv/ vcc3r3 = 3.3v - 70 100 a iq_25 quiescent current at 25 . vcc3r3 = 3.3v - 100 125 a vcc3r3 = 3.3v - 85 115 a iq_125 quiescent current at 125 . vcc3r3 = 3.3v - 125 170 a cout output external capacitor. 0.1 1 - f esr allowable effective series resistance of external capacitor. - 0.5 1
asix electronics corporation 26 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.2 power consumption symbol description conditions min typ max unit i vcck current consumption of vcck 47.5 ma i vcc18a current consumption of vcc18a 39.3 ma i vcc3io current consumption of vcc3io 16.6 ma i vcc33a current consumption of vcc33a_h + vcc33a_pll + vcc33a_pll operating at ethernet 100mbps full duplex mode and usb high speed mode 35.4 ma i vcck current consumption of vcck 44.3 ma i vcc18a current consumption of vcc18a 39.3 ma i vcc3io current consumption of vcc3io 12.9 ma i vcc33a current consumption of vcc33a_h + vcc33a_pll + vcc33a_pll operating at ethernet 100mbps full duplex mode and usb full speed mode 28.7 ma i vcck current consumption of vcck 19.3 ma i vcc18a current consumption of vcc18a 6.3 ma i vcc3io current consumption of vcc3io 8.3 ma i vcc33a current consumption of vcc33a_h + vcc33a_pll + vcc33a_pll operating at ethernet 10mbps full duplex mode and usb high speed mode 38.8 ma i vcck current consumption of vcck 14.9 ma vcc18a current consumption of vcc18a 6.2 ma i vcc3io current consumption of vcc3io 4.9 ma i vcc33a current consumption of vcc33a_h + vcc33a_pll + vcc33a_pll operating at ethernet 10mbps full duplex mode and usb full speed mode 32.3 ma i vcck current consumption of vcck 2.0 a i vcc18a current consumption of vcc18a 49.3 a i vcc3io current consumption of vcc3io 0.7 ma i vcc33a current consumption of vcc33a_h + vcc33a_pll + vcc33a_pll suspend (the embedded ethernet phy is powered down) 0.2 ma i vcck current consumption of vcck 19 ma i vcc18a current consumption of vcc18a 3.4 ma i vcc3io current consumption of vcc3io 8.5 ma i vcc33a current consumption of vcc33a_h + vcc33a_pll + vcc33a_pll AX88172A in usb full speed, rev-mii operation and internal phy power save (bmcr[11] bit = 1) 30.9 ma i vcck current consumption of vcck 22 ma i vcc18a current consumption of vcc18a 3.4 ma i vcc3io current consumption of vcc3io 11.5 ma i vcc33a current consumption of vcc33a_h + vcc33a_pll + vcc33a_pll AX88172A in usb high speed, rev-mii operation and internal phy power save (bmcr[11] bit = 1) 36.9 ma 1.8v 100 ma i device power consumption of ax88772a/AX88172A chip only 3.3v (excluding vcc3r3) 70 ma i system power consumption of ax88x72a demo board total of 3.3v (including vcc3r3 regulator supplies 1.8v to vcck and vcc18a) 220 ma table 3 : power consumption
asix electronics corporation 27 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.3 power-up sequence at power-up, the ax88772a/AX88172A requires the vcc3r3/vcc3io/vcc3a3/vcc33a_h/ vcc33a_pll power supply to rise to nominal operating voltage within trise3 and the v18f/vcck/vcc18a power supply to rise to nominal operating voltage within trise2. symbol parameter condition min typ max unit t rise3 3.3v power supply rise time from 0v to 3.3v 0.5 - 10 ms t rise2 1.8v power supply rise time from 0v to 1.8v - - 10 ms t delay32 3.3v rise to 1.8v rise time delay -5 - 5 ms 0v 3.3v trise3 0v 1.8v trise2 tdelay32 v18f/vcck/vcc18a vcc3r3/vcc3io/vcc3a3 /vcc33a_h/ vcc33a_pll
asix electronics corporation 28 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4 ac timing characteristics notice that the following ac timing specifications for output pins are based on c l (output load)=50pf. 9.4.1 clock timing xtl12p t p_xtl12p t h_xtl12p t l_xtl12p symbol parameter condition min typ max unit t p_xtl12p xtl12p clock cycle time - 83.33 - ns t h_xtl12p xtl12p clock high time - 41.6 - ns t l_xtl12p xtl12p clock low time - 41.6 - ns xtl25p t p_xtl25p t h_xtl25p t l_xtl25p symbol parameter condition min typ max unit t p_xtl25p xtl25p clock cycle time - 40.0 - ns t h_xtl25p xtl25p clock high time - 20.0 - ns t l_xtl25p xtl25p clock low time - 20.0 - ns 9.4.2 reset timing xtl12p reset_n symbol description min typ max unit trst reset pulse width after xtl12p is running 60 - 120000 xtl12p clock cycle* *: if the system applications require using hardware reset pin, reset_n, to reset ax88772a/AX88172A during device initialization or normal operation after vbus pi n is asserted, the above timing spec (min=5 s, max=10ms) of reset_n should be met. v ih v il v ih v il trs t
asix electronics corporation 29 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.3 serial eeprom timing th ts tlcs tlcs thcs tscs tod tdv tclk tcl tclk tcl tch tch eeck eedio (as output) eecs eedio (as input) symbol description min typ max unit tclk eeck clock cycle time - 5120 - ns tch eeck clock high time - 2560 - ns tcl eeck clock low time - 2560 - ns tdv eedio output valid to eeck rising edge time 2560 - - ns tod eeck rising edge to eedio output delay time 2562 - - ns tscs eecs output valid to eeck rising edge time 2560 - - ns thcs eeck falling edge to eecs invalid time 7680 - - ns tlcs minimum eecs low time 23039 - - ns ts eedio input setup time 20 - - ns th eedio input hold time 0 - - ns
asix electronics corporation 30 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.4 mii timing tth tts ttcl k ttcl ttcl k ttcl ttch ttch txclk txen / txd[3:0] symbol description min typ max unit ttclk txclk clock cycle time *1 - 40.0 - ns ttch txclk clock high time *2 - 20.0 - ns ttcl txclk clock low time *2 - 20.0 - ns tts txd [3:0], txen setup to rising txclk 23.0 - - ns tth txd [3:0], txen hold from rising txclk 7.0 - - ns trh trs trc lk trc l trc lk trc l trc h trc h rxclk rxdv / rxd[3:0] symbol description min typ max unit trclk rxclk clock cycle time *1 - 40.0 - ns trch rxclk clock high time *2 - 20.0 - ns trcl rxclk clock low time *2 - 20.0 - ns trs rxd [3:0], rxdv setup to rising rxclk 5.0 - - ns trh rxd [3:0], rxdv hold from rising txclk 3.5 - - ns *1: for 10mbps, the typical value of ttclk and trclk shall scale to 400ns. *2: for 10mbps, the typical value of ttch, ttcl, trch, and trcl shall scale to 200ns.
asix electronics corporation 31 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.5 station management timing th ts tod tcl k tcl tcl k tcl tch tch m dc m di o (as o utp ut) m di o (as inp ut) mac mode with mii: mdc=output symbol description min typ max unit tclk mdc clock cycle time - 640 - ns tch mdc clock high time - 320 - ns tcl mdc clock low time - 320 - ns tod mdc clock rising edge to mdio output delay 0.5 - - tclk ts mdio data input setup time 125 - - ns th mdio data input hold time 0 - - ns phy/dual-phy mode with re verse-mii/rmii: mdc=input symbol description min typ max unit tclk mdc clock cycle time - 320 - ns tch mdc clock high time - 160 - ns tcl mdc clock low time - 160 - ns tod mdc clock rising edge to mdio output delay 0 - 300 ns ts mdio data input setup time 10 - - ns th mdio data input hold time 10 - - ns
asix electronics corporation 32 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.6 reverse-mii timing tr h tr s tc lk tc l tc lk tc l tc h tc h rxclk rxd[3:0] rxdv symbol description min typ max unit tclk clock cycle time - 40.0 - ns tch clock high time - 20.0 - ns tcl clock low time - 20.0 - ns trs rxd [3:0], rxdv setup to rising rx clk 10.0 - - ns trh rxd [3:0], rxdv hold from rising rx clk 10.0 - - ns tth tts tc lk tc l tc lk tc l tc h tc h txclk txd[3:0] txen symbol description min typ max unit tts txd [3:0], txen setup to rising tx clk 11.0 - - ns tth txd [3:0], txen hold from rising tx clk 2.0 - - ns
asix electronics corporation 33 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.7 reverse-rmii timing tref_rh tref_rs tref_clk tref_cl tref_clk tref_cl tref_ch tref_ch refclk_i rxd[1:0] crsdv symbol description min typ max unit tref_clk clock cycle time - 20.0 - ns tref_ch clock high time - 10.0 - ns tref_cl clock low time - 10.0 - ns tref_rs rxd [1:0], crsdv setup to rising refclk_i 4.0 - - ns tref_rh rxd [1:0], crsdv hold from rising refclk_i 2.0 - - ns tref_th tref_ts tref_clk tref_cl tref_clk tref_cl tref_ch tref_ch refclk_i txd[1:0] txen symbol description min typ max unit tref_ts txd [1:0], txen setup to rising refclk_i 4.0 - - ns tref_th txd [1:0], txen hold from rising refclk_i 2.0 - - ns
asix electronics corporation 34 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.8 i2c interface timing i2c master controller timing table: symbol parameter standard mode (typ) fast mode (typ) unit fclk i2c_scl clock frequency. 100 400 khz thigh high period of the i2c_scl clock. 4.0 1.0 s tlow low period of the i2c_scl clock. 6.0 1.5 s tsu_sta setup time for a repeated start (sr) condition. 4.0 1.0 s thd_sta hold time of (repeated) start (s) condition. after this period, the first clock pulse is generated 4.0 1.0 s tsu_dat data setup time. 2.0 0.5 s thd_dat data hold time. 4.0 1.0 s tsu_sto data setup time for stop (p) condition. 4.0 1.0 s tbuf bus free time between a stop and start condition. note 1 note 1: it will be much greater than 22us because severa l factors can influence this pa rameter such as usb system utilization, the cbw structure, and high/full speed, etc. i2c slave controller timing table: symbol parameter min typ max unit fclk i2c_scl clock frequency. - - 390 khz high period of the i2c_scl clock in fast mode. 0.6 - - s thigh high period of the i2c_scl clock in standard mode. 4.0 - - s tlow low period of the i2c_scl clock. 0.4 - - s tsu_sta setup time for a repeated start (sr) condition. 1 - - tsys_clk (note 2) thd_sta hold time of (repeated) start (s) condition. after this period, the first clock pulse is generated 3 - - tsys_clk tsu_dat data setup time. 3 - - tsys_clk thd_dat data hold time. 0.4 - - s tsu_sto data setup time for stop (p) condition. 1 - - tsys_clk tbuf bus free time between a stop and start condition. - - - note 2: tsys_clk =33.33ns for 30mhz operating system clock.
asix electronics corporation 35 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.9 spi interface timing note: above diagram only shows setup and hold time relationshi p of spi pins in mode 0. for the remaining 3 modes, clock polarity is reversed. spi master controll er timing table: symbol description min typ max unit fclk spi_sclk clock frequency. - fsys_clk/ (spibrr+1)*2 5 mhz (note 3) tl setup time of spi_ss to the first spi_sclk edge. - 0.5 - tclk (note 3) th hold time of spi_ss after the last spi_sclk edge. - 0.5 - tclk tdly spi_mosi data valid time after spi_sclk edge. - - 1 tsys_clk (note 4) dsu spi_miso data setup time befo re spi_sclk edge. 2 - - tsys_clk dhd spi_miso data hold time after spi_sclk edge. 4 - - tsys_clk tl minimum idle time between transfers (minimum spi_ss high time). note 5 internal time base period. - 0.5 - tclk note 3: fsys_clk is the operating system clock frequency 30mhz. the spibrr is spi baud rate register. tclk = 1/fclk. note 4: tsys_clk =1/ fsys_clk =33.33 ns. note 5: it will be much greater than 22us because several factors can influence this parameter, such as usb system utilization, the cbw structure, and high/full speed ,etc.
asix electronics corporation 36 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller spi slave controller timing table: symbol description min typ max unit fclk spi_sclk clock frequency. - - 2 mhz tdly spi_miso data valid time after spi_sclk edge. - - 3 tsys_clk dsu spi_mosi data setup time befo re spi_sclk edge. 1 - - tsys_clk dhd spi_mosi data hold time after spi_sclk edge. 3 - - tsys_clk sssu spi_ss setup time before spi_sclk edge. 2 - - tsys_clk sshd spi_ss hold time after spi_sclk edge. 4 - - tsys_clk ssidle spi_ss negation to next spi_ss active time 2 - - tsys_clk
asix electronics corporation 37 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.10 10/100m ethernet phy interface timing 10/100m ethernet phy transmitter waveform and spec: symbol description condi tion min typ max units peak-to-peak differential output voltage 10base-t mode 4.4 5 5.6 v vtxa *2 peak-to-peak differential output voltage 100base-tx mode 1.9 2 2.1 v tr / tf signal rise / fall time 100base-tx mode 3 4 5 ns output jitter 100base-tx mode, scrambled idle signal - - 1.4 ns vtxov overshoot 100base-tx mode - - 5 % 10/100m ethernet phy receiver spec: symbol description condi tion min typ max units receiver input impedance 10 - - k differential squelch voltage 10base-t mode 300 400 500 mv common mode input voltage 2.97 3.3 3.63 v maximum error-free cable length 100 - - meter tr: from 10% to 90% +vtxov 0v +vtxa
asix electronics corporation 38 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 9.4.11 usb transceiver interface timing vcc33a_h/ vcc33a_pll= 3.0 ~ 3.6 v. static characteristic fo r analog i/o pins (dp/dm): symbol parameter conditions min typ max unit usb 2.0 transceiver (hs) input levels (differential receiver) v hsdiff high speed differential input sensitivity |v i (dp) ?v i (dm) | measured at the connection as an application circuit. 300 - - mv v hscm high speed data signaling common mode voltage range -50 - 500 mv squelch detected - - 100 mv v hssq high speed squelch detection threshold no squelch detected 200 - - mv output levels (differential) v hsoi high speed idle level output voltage -10 - 10 mv v hsol high speed low level output voltage -10 - 10 mv v hsoh high speed high level output voltage -360 - 400 mv v chirpj chirp-j output voltage 700 - 1100 mv v chirpk chirp-k output voltage -900 - -500 mv resistance r drv driver output impedance equivalent resistance used as internal chip 40.5 45 49.5 ohm termination v term termination voltage for pull-up resistor on pin rpu 3.0 - 3.6 v usb 1.1 transceiver (fs/ls) input levels (differential receiver) v di differential input sensitivity | v i (dp) ? v i (dm) | 0.2 - - v v cm differential common mode voltage 0.8 - 2.5 v input levels (single-ended receiver) v se single ended receiver th reshold 0.8 - 2.0 v output levels v ol low-level output voltage 0 - 0.3 v v oh high-level output voltage 2.8 - 3.6 v
asix electronics corporation 39 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller dynamic characteristic fo r analog i/o pins (dp/dm): symbol parameter conditions min typ max unit driver characteristic high-speed mode t hsr high-speed differential rise time - 500 - - ps t hsf high-speed differential fall time - 500 - - ps full-speed mode t fr rise time of dp/dm c l =50pf; 10 to 90% of |v oh - v ol | 4 - 20 ns t ff fall time of dp/dm c l =50pf; 90 to 10% of |v oh - v ol | 4 - 20 ns t frma differential rise/fall time matching ( t fr / t ff ) excluding the first transition from idle mode 90 - 110 % v crs output signal crossover voltage excluding the first transition from idle mode 1.3 - 2.0 v driver timing high-speed mode driver waveform requirement see eye pattern of template 1 follow template 1 described in usb rev 2.0 spec. ( http://www.usb.org/ developers/docs ) full-speed mode vi, fse 0, oe to dp, dn propagation delay for detailed description of vi, fse 0 and oe, please refer to usb rev 1.1specification. - - 15 ns receiver timing high-speed mode data source jitter and receiver jitter tolerance see eye pattern of template 4 follow template 4 described in usb rev 2.0 spec. ( http://www.usb.org/ developers/docs ) full-speed mode t plh (rcv) t phl (rcv) receiver propagation delay (dp; dm to rcv) for detailed description of rcv, please refer to usb rev 1.1specification. - - 15 (note) ns t plh (single) t phl (single) receiver propagation delay (dp; dm to vop, von) - - - 15 (note) ns note: full-speed timing diagram
asix electronics corporation 40 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 10.0 package information 10.1 ax88772a 64-pin lqfp package b e d hd e he pin 1 a2 a1 l l1 a millimeter symbol min typ max a1 0.05 - 0.15 a2 1.35 1.40 1.45 a - - 1.60 b 0.13 0.18 0.23 d 7.00 e 7.00 e - 0.40 - hd 9.00 he 9.00 l 0.45 0.60 0.75 l1 - 1.00 ref - 0 3.5 7
asix electronics corporation 41 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 10.2 AX88172A 80-pin tqfp package b e d hd e he pin 1 a2 a1 l l1 a millimeter symbol min typ max a1 0.05 - 0.15 a2 0.95 1.00 1.05 a - - 1.20 b 0.13 0.16 0.23 d 10.00 e 10.00 e - 0.4 bsc - hd 12.00 he 12.00 l 0.45 0.60 0.75 l1 - 1.00 ref - 0 3.5 7
asix electronics corporation 42 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 11.0 ordering information part number description ax88772alf ax88772a: product name (64 pin). l: lqfp package. f: lead free. AX88172Atf AX88172A: product name (80 pin). t: tqfp package. f: lead free.
asix electronics corporation 43 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 12.0 revision history revision date comment v0.7 2007/8/13 initial release. v1.0 2007/11/21 1. update the power consumption information and add i device and i system in section 9.2. 2. move the thermal characteristics information from section 9.2 to section 9.1.2 and update the thermal characteristics information. 3. update the tj junction operating temperature information in section 9.1.2, 9.1.4, 9.1.5 and 9.1.6. 4. update the reset timing information in section 9.4.2. v1.1 2007/12/24 1. update some information in section 9.1.6.
asix electronics corporation 44 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller appendix a. default wol ready mode please contact asix for receiving ?ax 88x72a full datasheet? which contains de tailed description of appendix a.
asix electronics corporation 45 ax88772a/AX88172A low-pin-count usb 2.0 to 10/100m fast ethernet controller 4f, no.8, hsin ann rd., hsinchu science park, hsinchu, taiwan, r.o.c. tel: +886-3-5799500 fax: +886-3-5799558 email: support@asix.com.tw web: http:// www.asix.com.tw

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